1. Field of the Invention
The present invention relates to a band gap reference. More particularly, the present invention relates to a band gap reference which can operate with 2.5 volt transistors and provide a constant reference voltage during power supply voltage variations and temperature changes.
1. Description of the Related Art
I. Prior Art Circuit of FIG. 1
FIG. 1 shows components used to form a prior art band gap reference. The band gap reference includes three variable current sources I.sub.1, I.sub.2 and I.sub.3 composed of PMOS transistors. The gates of the transistors forming the current sources I.sub.1 -I.sub.3 are connected together. With the same voltage at the gate of all three current sources I.sub.1, I.sub.2 and I.sub.3, the total current supplied by each current source will be substantially equal.
The band gap reference circuit of FIG. 1 also includes three diodes D.sub.1, D.sub.2 and D.sub.3, each composed of a PNP bipolar transistor with a base and collector connected to V.sub.SS or ground. Diode D.sub.2 is indicated as 10 times larger than diode D.sub.1. D.sub.2 may be composed of 10 parallel connected transistors each having the same size as the single transistor forming D.sub.1. As such, the current through each of the 10 diodes D.sub.2 will be 1/10 the current through D.sub.1, since I.sub.1 and I.sub.2 will be equal. The difference in voltage across diodes D.sub.1 and D.sub.2 will have a relation dependent on temperature as can be seen from the current to voltage relation for a silicon diode which is as follows: EQU I=Io(.epsilon..sup.V/2VT -1)
VT is kT/q where T is temperature in Kelvin, k is Boltzmann's constant, and q is the charge on an electron. Io is the reverse saturation current for the diode.
The circuit of FIG. 1 functions to maintain an equal voltage at nodes n1 and n2. Initially, with D.sub.2 larger than D.sub.1 and equal current from I.sub.1 and I.sub.2, the node n1 will try to go lower than the node n2, and current through I.sub.1, I.sub.2 and I.sub.3 will increase. Current will increase until the voltage across resistor R.sub.1 balances the voltage difference between D.sub.1 and D.sub.2 as controlled by NMOS transistors T.sub.1 and T.sub.2. With node n2 voltage later increasing above n2, current in I.sub.1, I.sub.2 and I.sub.3 will decrease until the voltage across R.sub.2 balances the voltage difference between D.sub.1 and D.sub.2. A more detailed description of the operation of the circuit of FIG. 1 is described in the following paragraphs.
In operation, we initially assume that node n1 is below the voltage of node n2 since D.sub.2 is larger than D.sub.1. The current sources I.sub.1 and I.sub.2 will carry the same current, since their gates are connected together and the current source transistors will be in saturation mode. Transistors T.sub.1 and T.sub.2 which are the same size and connected in a source follower configuration will also carry the same current. With node n2 above n1, transistor T.sub.2, connected in a cascode configuration, will try to sink more current to pull down node n3. The node n3 voltage will be reduced until the voltage on n1 and n2 are equal.
Note that a cascode transistor is a transistor defined by being turned on and off by varying voltage applied to the source with the gate voltage substantially fixed when the transistor is an NMOS device. With the source voltage decreasing relative to the gate, the cascode transistor will turn on to a greater extent. With the source voltage increasing relative to the gate, the cascode transistor will turn off to a greater extent.
If n1 goes above n2, T.sub.2 will sink less current than T.sub.1. Node n3 will then be pulled up, reducing current supplied from I.sub.2. Node n3 voltage will increase until the voltage on n1 and n2 are substantiallyequal.
In summary, the relationship of node n1 to node n2 determines increasing or decreasing current through current sources I.sub.1, I.sub.2 and I.sub.3.
After the balance point is reached, the current from current sources I.sub.1, I.sub.2, or I.sub.3 will vary in proportion to temperature due to the variation of the difference in voltage across diodes D.sub.1 and D.sub.2 with temperature, as can be seen from the silicon diode equation above. The voltage difference will decrease with increasing temperature, so that with higher temperatures greater current will be provided from I.sub.1, I.sub.2 and I.sub.3. Current from I.sub.1, I.sub.2 and I.sub.3 will, thus, vary in proportion to temperature. The resistance R.sub.1 is set to control the average current supplied from the current sources I.sub.1, I.sub.2 and I.sub.3.
A resistor R.sub.3 and diode D.sub.3 connect the output V.sub.DIODE to ground. With the current of I.sub.3 increasing in proportion to temperature, the voltage across R.sub.2 will likewise increase with temperature. The voltage across the diode D.sub.3, however, will decrease with temperature variations. The D.sub.3 voltage will otherwise remain constant with temperature. The resistance of resistor R.sub.2 is chosen so that the voltage change with temperature across R.sub.2 will balance the voltage change with temperature across diode D.sub.3 so V.sub.DIODE will remain constant.
The circuit of FIG. 1 is referred to as a band gap reference because the voltage V.sub.DIODE will be substantially equal to the voltage across the p-n band gap of a diode. For silicon, V.sub.DIODE will be approximately 1.2 volts.
III. Prior Art Circuit of FIG. 2
FIG. 2 shows the band gap reference of FIG. 1 modified to include an inverter INV and transistor T.sub.3 to get the circuit out of a potential forbidden state at start up. After start up, node n3 may be high while transistors T.sub.1 and T.sub.2 remain off. The inverter INV will then pull down the gate of T.sub.3. Transistor T.sub.3 then applies additional current to the drain which raises n4 and so turns on transistors T.sub.1 and T.sub.2. Transistor T.sub.2 will then pull down n3 and turn on current sources I.sub.1 and I.sub.3. The inverter INV will then turn off.
IV. Prior Art Circuit of FIG. 3
FIG. 3 shows modifications to the band gap reference circuit of FIG. 2 to include transistors T.sub.4, T.sub.5 and T.sub.6 to limit variations in V.sub.DIODE with changes in V.sub.DD. In the circuit of FIGS. 1 and 2, since the gate and drain of the transistor forming current source I.sub.2 are connected, node n3 will be 1 vt below V.sub.DD (vt being a CMOS transistor threshold). Node n4 will be 1 vt above n2 since the drain and gate of transistor T.sub.2 are connected, and node n2 will be 1 vt above ground as set by the PNP transistor forming diode D.sub.1. However, with V.sub.DD changing n3 will change since it is 1 vt below V.sub.DD, but n4 being 2 vt above ground will not. Thus, current will vary in current source I.sub.1 relative to current source I.sub.2 because although I.sub.1 and I.sub.2 have the same respective gate and source voltages, their drain voltages will vary relative to each other depending on V.sub.DD variations. Accordingly, the current sources I.sub.1, I.sub.2 and I.sub.3 will not be equal and V.sub.DIODE will vary with V.sub.DD changes.
In the circuit of FIG. 3, node n3 will be 1 vt below V.sub.DD with the source and drain of transistor forming I.sub.2 tied together. Since the drain of transistor T.sub.4 is not tied to its gate, node n10 will not be at a fixed number of vt drops relative to ground. Since transistors T.sub.4 and T.sub.5 are connected in a source follower configuration, node n10 will be equal in voltage to node n3. In other words, the respective gate, source, and drain voltage of transistors forming I.sub.1 and I.sub.2 will be equal, so I.sub.1 and I.sub.2 are biased the same. Therefore the current from current sources I.sub.1, I.sub.2 and I.sub.3 will be equal.
However with low voltage circuits, such as a device using transistors made using a 2.5 volt semiconductor process technology, the maximum value for V.sub.DD may be lower than a value necessary for the circuit of FIG. 3 to function. For a 2.5 volt device, V.sub.DD will typically be 2.5 volts. In the circuit of FIG. 3, a 1 vt drop will be applied across the transistor for I.sub.2, the transistors T.sub.5 and T.sub.1 and the transistors for each of diodes D.sub.1, D.sub.2 and D.sub.3. Assuming a minimum vt is approximately 0.7 volts, the total voltage for four stacked transistors will be 2.8 volts. If temperature drops, however, the voltage vt can rise significantly. The typical room temperature vt for PMOS transistors may exceed 1.0 volts. Thus, the total voltage across four stacked transistors can easily exceed 3.0 volts.
The circuit of FIG. 2 has three stacked transistors, so it can use a V.sub.DD supply of 3.0 volts, but as indicated above, its current sources I.sub.1, I.sub.2 and I.sub.3 may vary relative to one another with V.sub.DD variations.